Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates

Abstract

In this thesis, we have first characterized candidates of the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). Then, we have chosen five candidates from the Round 2 and Round 3 submissions, namely SCREAM, AES-COPA, Minalpher, OCB, and AES-OTR. We first obtained the initial estimates of the Maximum Clock Frequency, Throughput, Area, and Critical path from the Basic Iterative High Speed Architecture. Then, we implemented the inner-round pipelining for all the selected algorithms to improve the Frequency and Throughput by reducing Critical path and processing multiple blocks of data simultaneously. We targeted the largest available FPGA in the student version of Xilinx ISE, i.e., Xilinx Virtex 6 XC6VLX75T-3FF784. Our results have demonstrated the improvement in the Clock Frequency by a factor varying from x1.28 for OCB to x1.84 for SCREAM, and the improvement in the Throughput to Area ratio (with Area expressed using LUTs) by a factor varying from x0.96 for Minalpher to x1.70 for SCREAM.