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Differential Power Analysis on Light Weight Implementations of Block Ciphers

Show simple item record Yalla, Panasayya S.V.V.K
dc.creator Yalla, Panasayya S.V.V.K 2009-07-31 2009-09-28T16:27:12Z NO_RESTRICTION en_US 2009-09-28T16:27:12Z 2009-09-28T16:27:12Z
dc.description.abstract There is a growing interest in light weight implementation of cryptographic algorithms for low-resource ubiquitous computing devices such as a wireless sensor nodes (WSN) or radio frequency identification (RFID) tags. Most light weight cryptographic implementations are targeted to application specific integrated circuits (ASIC). However, ASICs have a high non-recurring engineering cost and longer time to market. Even though field programmable gate arrays (FPGA) are reconfigurable and have low non-recurring engineering cost, they consume more power than ASICs. Power consumption is a primary concern for light weight cryptographic applications. With the development of low-cost, low-power FPGAs for battery powered devices, they are becoming an interesting target for light weight cryptography (LWC). In this thesis we describe compact architectures of AES, Camellia, xTEA, HIGHT and Present are implemented on low-cost Xilinx Spartan3 FPGAs. Different optimization techniques are employed to minimize the area consumption by smart use of the Configurable Logic Block (CLB) structure in FPGAs. All the cipher implementations are light weight but with full strength security i.e. not 80-bit but 128-bit key length. Furthermore, differential power analysis (DPA) attacks are performed on these implementations to investigate their "natural", i.e. without any countermeasures resistance to this form of attack.
dc.language.iso en_US en_US
dc.subject DPA en_US
dc.subject ASIC en_US
dc.subject FPGA en_US
dc.subject LWC en_US
dc.title Differential Power Analysis on Light Weight Implementations of Block Ciphers en_US
dc.type Thesis en Master of Science in Computer Engineering en_US Master's en Computer Engineering en George Mason University en

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