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Issues of ESD protection in nano-scale CMOS

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dc.contributor.advisor Ioannou, Dimitris E. Yang, Yang
dc.creator Yang, Yang 2010-06-28 2010-11-02T11:47:47Z NO_RESTRICTION en_US 2010-11-02T11:47:47Z 2010-11-02
dc.description.abstract Aggressive downsizing of individual transistors continues to improve the perfor- mance of integrated circuits. However, as the transistors get smaller, they become more vulnerable to damage by high current and high voltage Electrostatic Discharges (ESD). As technology scales down, among other things, new materials such as high-k gate dielectrics are incorporated into the modern chip fabrication technologies and Silicon-on-Insulator (SOI) technology is gaining acceptance. These technology ad- vances make ESD protection of silicon chips ever more necessary and challenging. Consequently, the present dissertation focuses on ESD related issues in nano-scale CMOS technologies. The thesis begins with the investigation of high-k gate dielectric breakdown under ESD-like stress. The stress con guration for transistors in the input receiver will be considered rst. It is con rmed that high-k gate oxide breakdown is catastrophic under ESD-like stress. Using the constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs are compared under di erent stress polarities, in order to identify the worst case scenario. The results are also compared with SiON gate dielectric devices. Next, high-k gate breakdown in the output driver is explored. The results imply that the input receiver is more susceptible (than output driver) to failure due to ESD induced gate dielectric breakdown. Mea- surement results also show that VBD obtained by the transmission line pulsing method (TLP) is only slightly smaller than that obtained by the CVS method. Methodologies to improve the breakdown immunity are then proposed with the support of experi- mental results. The dissertation then focuses on the degradation of NMOSFETs with high-k gate under non-destructive ESD-like stress. For the stress con guration emulating the output driver, little degradation was observed until the device failed by drain-to- source lamentation. By contrast, for the stress con guration emulating the input receiver, degradations of threshold voltage (Vt), drain saturation current (Idsat) and Si/gate oxide interface were observed. The degradations increase with the e ective gate oxide thickness and are more severe under positive stress polarity. Di erent from Positive Bias Temperature Instability (PBTI) stress, the threshold voltage shift depends on temperature rather weakly, indicating a new dominant charge trapping mechanism active on the time scale of ESD events. These results are then compared with those obtained for transistors with SiON gate dielectric. In addition to Vt, Idsat and interface degradation, the impact of the stress on the gate leakage current and on the subsequent PBTI degradation kinetics is also studied. Finally, the dissertation presents a thorough investigation of the eld e ect diode (FED) with the aim to explore its potential for ESD protection applications in SOI technology. It is shown that the doping type and concentration under the two gates has an important impact on the device operation. By careful sizing and doping, FED devices with reasonable breakdown voltage values can be achieved at gate voltage values compatible with the latest technology.
dc.language.iso en_US en_US
dc.subject electrostatic discharge (esd) en_US
dc.subject field effect diode en_US
dc.subject gate dielectric breakdown en_US
dc.subject high-k gate en_US
dc.title Issues of ESD protection in nano-scale CMOS en_US
dc.type Dissertation en Doctor of Philosophy Electrical and Computer Engineering en_US Doctoral en Electrical and Computer Engineering en George Mason University en

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