Abstract:
Field Programmable Gate Array(FPGAs) are used as a common platform for almost any
type of design due to an increase in their logic capacity and various features such as DSP
blocks, embedded processors, etc. A cryptographic algorithm implemented on FPGAs leaks
data sensitive information through side channels such as power consumption, time taken for
computations, temperature, etc. Many side-channel cryptanalysis methods exist to attack
the physical implementation of cryptographic algorithms, thus rendering the algorithms
insecure. One branch of side-channel attack is Di erential Power Analysis (DPA); where
the attack is based on information gained from the power consumption of the cryptosystem.
Recently, the Research Center for Information (RCIS) of AIST and Tohoku University
developed the Side Channel Attack Standard Evaluation Board (SASEBO) as a common
platform for evaluating side channel attacks. There are two FPGAs on a SASEBO board,
a cryptographic FPGA - where the algorithm is implemented and a control FPGA - which
communicates the data between the software (SASEBO Waveform Acquisition) and the
cryptographic FPGA in an e cient manner. Sasebo Waveform Acquisition interacts with
the hardware for processing data and collecting power traces for a DPA attack.
The current interface between the control and cryptographic FPGA on the SASEBO-GII
board is used to implement a block cipher and a hash algorithm. However, as the standard
hardware interface proposed by the Cryptographic Engineering Research Group (CERG) of
George Mason University has a di erent protocol for block ciphers and hash functions, the
algorithms could not be directly integrated with the SASEBO-GII interface. This thesis
focuses on designing a new interface, with modi cations made to the original SASEBO
waveform acquisition software and the hardware on the control FPGA to interact with the
protocol of CERG-GMU. The data communication between the software and hardware with
implementations of lightweight block cipher was tested successfully on the modi ed 8-bit
interface. Also, results from the DPA attack on AES on both the original SASEBO-GII
interface and the modi ed interface are discussed.
