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IPsec Implementation in Embedded Systems for Partial Recon gurable Platforms

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dc.contributor.advisor Kaps, Jens-Peter
dc.contributor.author Salman, Ahmad
dc.creator Salman, Ahmad
dc.date 2011-05-20
dc.date.accessioned 2011-06-01T15:13:50Z
dc.date.available NO_RESTRICTION en_US
dc.date.available 2011-06-01T15:13:50Z
dc.date.issued 2011-06-01
dc.identifier.uri http://hdl.handle.net/1920/6394
dc.description.abstract Internet Protocol Security (IPsec) provides essential security against attacks on data transmitted over the Internet through di erent security services provided by cryptographic algorithms like encryption modules and hash functions. Due to the importance of IPsec, it has been implemented in hardware and software with di erent designs and parameters to suit di erent platforms and provide better solutions. Among the popular implementations of IPsec in hardware are those that target FPGA platforms because of the exibility they o er the designer, ease of programming and high speeds that cannot be achieved through software. Due to the fact that FPGAs are resource limited devices, even e cient imple- mentations of IPsec with all the services it provides might not t on low cost devices or low area devices that are meant for light weight implementations. A solution to this prob- lem can be Partial Recon guration which allows some IPsec services to be available in the system and the remaining services can be recalled when needed by an application. Partial Recon guration is a con guration method for FPGAs that allows certain portions of the device to be recon gured during run-time without a ecting other portions in the system or their functionality. In this thesis we will investigate the e ect of implementing IPsec services using Partial Recon guration in terms of speed, area and recon guration time. For that, we built an embedded system controlled through an embedded processor to provide self recon guration of the system through a software application. We also imple- mented di erent versions of the embedded system using Microblaze and PowerPC embedded processors targeting two di erent platforms (Virtex-4 and Virtex-II-Pro) to perform thor- ough testing on the proposed design and analyze the results. en_US
dc.language.iso en_US en_US
dc.subject Partial Reconfiguarion en_US
dc.subject Embedded en_US
dc.subject FPGA en_US
dc.subject SHA - 256 en_US
dc.subject IPsec en_US
dc.subject AES en_US
dc.title IPsec Implementation in Embedded Systems for Partial Recon gurable Platforms en_US
dc.type Thesis en
thesis.degree.name Masters in Computer Engineering en_US
thesis.degree.level Master's en
thesis.degree.discipline Computer Engineering en
thesis.degree.grantor George Mason University en


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