Abstract:
In 2007, the National Institute of Standards and Technology (NIST) announced a public
competition to develop a new cryptographic hash algorithm to become the SHA-3
standard. This algorithm should allow flexibility in the design tradeoff decisions between
performance and circuit area. This study evaluated two SHA-3 Round 2 Candidate
Algorithms, Blue Midnight Wish and CubeHash, to define their performance space in
FPGA hardware. High throughput designs were created using multi-message techniques,
and single-message Basic Iterative and Folded techniques were applied to find designs of
relatively low area. The results show a large performance range for both algorithms, but
the fine granularity achieved with parallel cores of CubeHash is superior to the inflexible
pipelined architecture of Blue Midnight Wish.
