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Fair and Comprehensive Comparison of Hardware Performance of SHA-3 Round 2 Candidates Using FPGAs

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dc.contributor.advisor Gaj, Kris
dc.contributor.author Homsirikamol, Ekawat
dc.creator Homsirikamol, Ekawat
dc.date 2010-07-30
dc.date.accessioned 2010-11-01T18:34:16Z
dc.date.available NO_RESTRICTION en_US
dc.date.available 2010-11-01T18:34:16Z
dc.date.issued 2010-11-01
dc.identifier.uri https://hdl.handle.net/1920/6018
dc.description.abstract In 2007, National Institute of Standards and Technology has announced a contest for a new American cryptographic hash function standard, called SHA-3. At the time of writing, after eliminating 37 algorithms in Round 1, due to security and performance weaknesses, only 14 Round 2 candidate algorithms remain in the competition. A comprehensive methodology for fair comparison of hash algorithms competing in the SHA-3 contest from the point of view of hardware performance in FPGAs has been proposed in this thesis. Based on this methodology, hardware designs optimized for the maximum throughput to area ratio have been developed for all Round 2 SHA-3 candidates. The obtained results have been compared with results from other groups. In our study, only three candidates, namely CubeHash, Keccak and Lu a, have consistently outperformed SHA-2 in terms of the throughput to area ratio for both 256 and 512 bits versions of all hash algorithms.
dc.language.iso en_US en_US
dc.subject FPGA en_US
dc.subject performance evaluation en_US
dc.subject SHA en_US
dc.subject hash en_US
dc.title Fair and Comprehensive Comparison of Hardware Performance of SHA-3 Round 2 Candidates Using FPGAs en_US
dc.type Thesis en
thesis.degree.name Master of Science Computer Engineering en_US
thesis.degree.level Master's en
thesis.degree.discipline Computer Engineering en
thesis.degree.grantor George Mason University en


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