Volgenau School of Engineering Graduate Research
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Browsing Volgenau School of Engineering Graduate Research by Author "Beheshti-Shirazi, Sayed Aresh"
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Item A Survey On Techniques Used for Designing Fault Tolerant and Process Variation Aware Memories and Caches(2020) Beheshti-Shirazi, Sayed AreshAggressive voltage and frequency scaling schemes applied to memory and cache structures, specially for memory systems fabricated in advanced and scaled geometry nodes that are severely affected by process variation,significantly increases the likelihood of read, write and access failures to/from memory cell array, and reduces the extent of frequency and voltage scaling. To remedy this problem, in the past decade, many researchers have investigated alternative and fault tolerant cache and memory organizations to mitigate the impact of process variation, and to reduce the failure rate of memory array in the results of voltage and frequency scaling. This paper discusses and compare many of such cache and memory design techniques.