Implementation and Evaluation of SAT-based Attacks on Hybrid STT-CMOS Circuits for Reverse Engineering
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Shenoy, Gaurav
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Abstract
The Integrated Circuit (IC) supply chain has been undergoing changes inorder to adapt and sustain to the growing costs and technology changes borne by the IC Design house . These changes also add vulnerabilities in the supply chain making the Intellectual Property (IP) susceptible to different forms of counterfieting and reverse engineering. An awareness of these threats have led to several new IC protection techniques to be proposed. This thesis comprises of the security analysis of layout level IC protection techniques such as programmable non-volatile Spin Transfer Torque-based Lookup Tables (STT-based LUTs) with the help of a strong SAT-based reverse engineering model. The partial netists using this IC protection technique is derived from ISCAS’85 and ISCAS’89 bench circuits. The technique is evaluated using various metrics against different parameters to determine its level of security and at the same time testing the SAT-based model’s reliability to crack them.
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Reverse engineering, SAT-based attacks, STT-CMOS hybrid