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Implementation of Log-Domain FFT Based LDPC Decoder on a GPU

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dc.contributor.advisor Mark, Brian L
dc.contributor.author Alqarni, Hanan
dc.creator Alqarni, Hanan
dc.date 2019-04-25
dc.date.accessioned 2019-07-02T00:23:36Z
dc.date.available 2019-07-02T00:23:36Z
dc.identifier.uri https://hdl.handle.net/1920/11492
dc.description.abstract Forward error correction enables reliable one-way communication over noisy channels by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance using belief propagation (BP) decoding. However, the computational complexity of a BP decoder is O(q2) operations for each checksum calculation, where q represents number of symbols in the underlying Galois field. The complexity is reduced by transforming the operations into the log and frequency domains. This thesis explores how a GPU implementation of a Log-domain FFT based LDPC decoder performs in comparison to a CPU implementation for regular MacKay construction. Numerical results show that the GPU implementation is about twice as fast as the CPU implementation. The thesis also studies the performance of GPU implementations of a Quasi-cyclic LDPC decoder for WIFI (IEEE 802.11n) and WIMAX (IEEE 802.16e) LDPC codes.
dc.language.iso en en_US
dc.subject LDPC en_US
dc.subject CUDA en_US
dc.subject GPU en_US
dc.subject decoding en_US
dc.subject sum-product en_US
dc.subject log-domain FFT en_US
dc.title Implementation of Log-Domain FFT Based LDPC Decoder on a GPU en_US
dc.type Thesis en_US
thesis.degree.name Master of Science in Computer Engineering en_US
thesis.degree.level Master's en_US
thesis.degree.discipline Computer Engineering en_US
thesis.degree.grantor George Mason University en_US


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