Landmine Detection Architectures And Their Implementation on FPGA

dc.contributor.advisorHintz, Kenneth J.
dc.contributor.authorCharankar, Nikita
dc.creatorCharankar, Nikita
dc.description.abstractThe data collected by the NIITEK GPR, high range resolution (HRR) ground-penetrating radar (GPR), results in a digitized raw video representing signals re ected at the surface of as well as internal to the landmine due to changes in impedances, materials dielectric properties. This digitized signal has to undergo several stages of preprocessing in order to produce a binary-valued- sequence. A part of this sequence contains a speci c length of string that is a characteristic of a mine pattern. The mine pattern, to be recognized from a longer string of processed GPR data, has to be presented to a landmine detector. The landmine detector not only detects the mine but also classi es them and discriminates the mines from clutter (noise). Three pattern recognizers, one reset Finite State Machine (FSM) and two behaviorally equivalent Parallel Correlators are designed to detect multiple landmines simultaneously. Alternative implementations of these processing modules are compared with respect to chip area in terms of number of slices (real-estate or chip area) and speed (processing time), as a function of the number of landmines to be simultaneously recognized. It is found that the reset FSM is smallest in size of all the architectures but the slowest, whereas, the rst Parallel Correlator is largest in size and the second Correlator, the fastest. An alternative pattern recognizer, a non-reset Finite State Machine, sometimes known as a Rabin-Scott Machine, is also analyzed in terms of chip area (slices) and speed(processing time) but with respect to the relevant parameter, the maximum number of states in FSM. It was apparent that both- the size as well as the speed of the FSM increases with the increase in the number of states.
dc.subjectLand mines
dc.subjectGround penetrating radar
dc.titleLandmine Detection Architectures And Their Implementation on FPGA
dc.typeThesis Engineering Mason University's of Science Electrical Engineering


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