Improving Performance and Mitigating Temperature Rise with Reconfigurable STT-NV Logic Based Functional Unit




Ashammagari, Adarsh Reddy

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Unavailability of functional units and their unequal activity makes them performance bottleneck and thermal hot spots units in general-purpose processors. This thesis proposes to use reconfigurable functional units to overcome these challenges. A selected set of complex functional units that might be under-utilized (i.e. have low temperature), such as a multiplier, divider, etc. are realized in a time multiplexed fashion using a shared programmable Look Up Table (LUT) based fabric. This allows for run-time reconfiguration and migration of the activity from functional units that are responsible for thermal hot spots (i.e. high temperature functional units) to the units that are less active. LUT based implementation also allows under-utilized functional units to be dynamically reconfigured to the functional units that are performance bottleneck (i.e. heavily utilized functional units) and hence improving performance. The programmable LUTs are realized using Spin Transfer Torque (STT) Magnetic technology (also called STT-NV) due to its zero leakage and CMOS compatibility. This thesis presents, the several developed power-thermal and performance-aware algorithms to most effectively reconfigure functional units at run-time. The results show significant performance improvement of 16% on average across standard benchmark. Also, reconfiguration reduces maximum temperature of functional units by up to 27° C and almost eliminates the thermal variation across functional units. This comes with almost 16% increase in functional units total power dissipation across SPECint benchmarks and almost 18% reduction in their power across SPECfp benchmarks.



Reconfigurable computing, Performance improvement, STT-NV LUT logic, Temperature reduction, Functional units