Evaluation of the Hardware Performance Space of SHA-3 Candidates Blue Midnight Wish and CubeHash Using FPGAs
| dc.contributor.advisor | Gaj, Kris | |
| dc.contributor.author | Lorentz, Robert | |
| dc.creator | Lorentz, Robert | |
| dc.date | 2011-12-09 | |
| dc.date.accessioned | 2012-01-31T15:48:49Z | |
| dc.date.available | NO_RESTRICTION | |
| dc.date.available | 2012-01-31T15:48:49Z | |
| dc.date.issued | 2012-01-31 | |
| dc.description.abstract | In 2007, the National Institute of Standards and Technology (NIST) announced a public competition to develop a new cryptographic hash algorithm to become the SHA-3 standard. This algorithm should allow flexibility in the design tradeoff decisions between performance and circuit area. This study evaluated two SHA-3 Round 2 Candidate Algorithms, Blue Midnight Wish and CubeHash, to define their performance space in FPGA hardware. High throughput designs were created using multi-message techniques, and single-message Basic Iterative and Folded techniques were applied to find designs of relatively low area. The results show a large performance range for both algorithms, but the fine granularity achieved with parallel cores of CubeHash is superior to the inflexible pipelined architecture of Blue Midnight Wish. | |
| dc.identifier.uri | https://hdl.handle.net/1920/7496 | |
| dc.language.iso | en_US | |
| dc.subject | FPGA | |
| dc.subject | SHA-3 | |
| dc.subject | Cryptography | |
| dc.subject | Hash Function | |
| dc.subject | Blue Midnight Wish | |
| dc.subject | Cube Hash | |
| dc.title | Evaluation of the Hardware Performance Space of SHA-3 Candidates Blue Midnight Wish and CubeHash Using FPGAs | |
| dc.type | Thesis | |
| thesis.degree.discipline | Computer Engineering | |
| thesis.degree.grantor | George Mason University | |
| thesis.degree.level | Master's | |
| thesis.degree.name | Masters in Computer Engineering |