Compact Implementations and Benchmarking of Two SHA-3 Finalists BLAKE and JH on FPGAs
| dc.contributor.advisor | Kaps, Jens-Peter | |
| dc.contributor.author | Vadlamudi, Susheel Choudary | |
| dc.creator | Vadlamudi, Susheel Choudary | |
| dc.date | 2012-01-20 | |
| dc.date.accessioned | 2012-02-23T15:42:16Z | |
| dc.date.available | NO_RESTRICTION | |
| dc.date.available | 2012-02-23T15:42:16Z | |
| dc.date.issued | 2012-02-23 | |
| dc.description.abstract | Security and message authentication play a crucial role in communications. The current hashing standards for message authentication are SHA-1 and SHA-2. Attacks on SHA-1 which show potential vulnerabilities of this algorithm were published in 2005. As SHA-2 is based on SHA-1 it might be vulnerable to the same attacks. National Institute of Standards and Technology (NIST) initiated a contest to determine a new American hash standard called SHA-3. After evaluating the initial 64 algorithms that were submitted, five algorithms were selected for the final round. The five finalists are: BLAKE, Grøestl, JH, Keccak and Skein. Security and performance in hardware as well as software were the key factors in choosing the five finalists. Evaluating the performance of these algorithms in resource constrained environments, like PDAs and smart phones is of major interest for mobile ubiquitous computing. New low-power Field Programmable Gate Arrays (FPGA), which are suitable for battery powered devices, have low non-recurring engineering cost and faster time to market than Application Specific Integrated Circuits (ASIC). We designed compact architectures for BLAKE and JH, targeting Xilinx low-cost Spartan-3 FPGAs. To achieve a good throughput to area ratio we developed different architectures, maintaining the design criteria of 800 slices, or 400-600 slices with one Block RAM, respectively, on Xilinx Spartan-3 devices. We compared the performance of our implementations by synthesizing them on several devices from Xilinx and Altera. Our compact implementations of BLAKE and JH outperform other published results in terms of throughput to area ratio. Considering the lightweight implementations of all the five finalists, BLAKE has the best performance and JH has an average performance. | |
| dc.identifier.uri | https://hdl.handle.net/1920/7527 | |
| dc.language.iso | en_US | |
| dc.subject | SHA-3 | |
| dc.subject | Blake and JH | |
| dc.subject | Compact Implementations | |
| dc.subject | SHA-3 on FPGAs | |
| dc.subject | Cryptography | |
| dc.subject | Hash Algorithms | |
| dc.title | Compact Implementations and Benchmarking of Two SHA-3 Finalists BLAKE and JH on FPGAs | |
| dc.type | Thesis | |
| thesis.degree.discipline | Computer Engineering | |
| thesis.degree.grantor | George Mason University | |
| thesis.degree.level | Master's | |
| thesis.degree.name | Masters in Computer Engineering |