Implementation and Benchmarking of Padding Units and HMAC for SHA-3 Candidates in FPGAs and ASICs
| dc.contributor.advisor | Gaj, Kris | |
| dc.contributor.author | Vyas, Ambarish | |
| dc.creator | Vyas, Ambarish | |
| dc.date | 2011-12-09 | |
| dc.date.accessioned | 2012-02-02T18:28:40Z | |
| dc.date.available | NO_RESTRICTION | |
| dc.date.available | 2012-02-02T18:28:40Z | |
| dc.date.issued | 2012-02-02 | |
| dc.description.abstract | In 2005, a major security flaw was discovered in Secure Hash Algorithm-1 (SHA-1), an NSA-designed cryptographic hash function, standardized by National Institute of Science and Technology (NIST) since 1995. Basic components in the more recent NIST standard SHA-2, introduced in 2002, are quite similar to SHA-1. As both functions are quite similar, it is prudent to expect that the equivalent attacks can be found against SHA-2 in the future. In retort to this possibility, NIST established a contest in search of a new cryptographic hash function family called SHA-3. Presently, the competition is in Round 3 evaluations, with 5 finalists shortlisted out of the 14 from Round 2. Various research groups from the cryptographic community are evaluating the performance of the finalists in hardware while trying their best to be fair in their design decisions. One of the topic of debate in the cryptographic community is whether padding should be included in hardware design or should it be done externally in software and not taken in consideration while evaluating the designs. We propose that padding should be included in the designs for fair evaluations, but should be designed intelligently so that the overall Throughput/Area ratio is not affected by an undesirable amount. In this thesis, we design and implement padding units for 5 Round 3 SHA 3 finalists for two hardware platforms, FPGAs and ASICs. We show that the worst effect of padding unit on the performance of the candidates does not exceed 18% in FPGAs and the overall ranking of the finalists does not change from the ranking derived from the architectures which do not support padding. Universal padding unit supporting all finalists and SHA-2 was designed for ASICs and the maximum area overhead due to the inclusion of a padding unit is around 9% with no effect on maximum clock frequency. This thesis also focuses on designing a Hash-based Message Authentication Code (HMAC) wrapper for all the SHA-3 finalists and SHA-2. | |
| dc.identifier.uri | https://hdl.handle.net/1920/7512 | |
| dc.language.iso | en_US | |
| dc.subject | FPGA | |
| dc.subject | Hash Function | |
| dc.subject | SHA-3 | |
| dc.subject | Cryptography | |
| dc.subject | Padding | |
| dc.subject | HMAC | |
| dc.title | Implementation and Benchmarking of Padding Units and HMAC for SHA-3 Candidates in FPGAs and ASICs | |
| dc.type | Thesis | |
| thesis.degree.discipline | Computer Engineering | |
| thesis.degree.grantor | George Mason University | |
| thesis.degree.level | Master's | |
| thesis.degree.name | Masters in Computer Engineering |