Compact Modeling of Multi Gate and Other Emerging Transistors

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dc.contributor.advisorIoannou, Dimitris E.
dc.contributor.authorDonizetti, Matthew Thomas
dc.creatorDonizetti, Matthew Thomas
dc.date2010-11-30
dc.date.accessioned2011-02-21T21:56:14Z
dc.date.availableNO_RESTRICTION
dc.date.available2011-02-21T21:56:14Z
dc.date.issued2011-02-21
dc.description.abstractWith the advent of multi gate and nanoscale fabrication techniques, several new transistor topographies have been proposed and manufactured in the past decade. In parallel, accurate and efficient compact models for these devices have been likewise developed. This paper summarizes the major topographies and their associated compact models with a focus toward computationally efficient models constructed for implementation in common modeling languages such as Verilog-A and SPICE. Common physical and mathematical modeling techniques have also been reviewed as has the evolution from simple multi gate devices to nanoscale structures.
dc.identifier.urihttps://hdl.handle.net/1920/6174
dc.language.isoen_US
dc.subjectBallistic
dc.subjectOverview
dc.subjectSolid state
dc.subjectBSIM
dc.subjectSurvey
dc.subjectSPICE
dc.titleCompact Modeling of Multi Gate and Other Emerging Transistors
dc.typeThesis
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorGeorge Mason University
thesis.degree.levelMaster's
thesis.degree.nameMaster of Science

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