Mason Archival Repository Service

Physics and Design of SOI FED Based Memory Cells

Show simple item record

dc.contributor.advisor Ioannou, Dimitris E.
dc.contributor.author Badwan, Ahmad Zuhdi
dc.creator Badwan, Ahmad Zuhdi
dc.date.accessioned 2016-04-19T19:29:45Z
dc.date.available 2016-04-19T19:29:45Z
dc.date.issued 2016
dc.identifier.uri https://hdl.handle.net/1920/10200
dc.description.abstract Memory arrays occupy a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory (6T-SRAM) and the single transistor dynamic random access memory (DRAM) cells both suffer from excessive leakage current. Therefore, there is a widely recognized need for urgent progress in memory technology to meet the increasing demand for highly for compact, high density and low power memory arrays.
dc.format.extent 118 pages
dc.language.iso en
dc.rights Copyright 2016 Ahmad Zuhdi Badwan
dc.subject Electrical engineering en_US
dc.subject DRAM en_US
dc.subject FED en_US
dc.subject field effect diode en_US
dc.subject SRAM en_US
dc.subject Thyristor en_US
dc.title Physics and Design of SOI FED Based Memory Cells
dc.type Dissertation en
thesis.degree.level Doctoral en
thesis.degree.discipline Electrical and Computer Engineering en
thesis.degree.grantor George Mason University en


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search MARS


Browse

My Account

Statistics