Physics and Design of SOI FED Based Memory Cells

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dc.contributor.advisorIoannou, Dimitris E.
dc.contributor.authorBadwan, Ahmad Zuhdi
dc.creatorBadwan, Ahmad Zuhdi
dc.date.accessioned2016-04-19T19:29:45Z
dc.date.available2016-04-19T19:29:45Z
dc.date.issued2016
dc.description.abstractMemory arrays occupy a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory (6T-SRAM) and the single transistor dynamic random access memory (DRAM) cells both suffer from excessive leakage current. Therefore, there is a widely recognized need for urgent progress in memory technology to meet the increasing demand for highly for compact, high density and low power memory arrays.
dc.format.extent118 pages
dc.identifier.urihttps://hdl.handle.net/1920/10200
dc.language.isoen
dc.rightsCopyright 2016 Ahmad Zuhdi Badwan
dc.subjectElectrical engineering
dc.subjectDRAM
dc.subjectFED
dc.subjectField effect diode
dc.subjectSRAM
dc.subjectThyristor
dc.titlePhysics and Design of SOI FED Based Memory Cells
dc.typeDissertation
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorGeorge Mason University
thesis.degree.levelDoctoral

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