A Survey On Techniques Used for Designing Fault Tolerant and Process Variation Aware Memories and Caches
Date
2020
Authors
Beheshti-Shirazi, Sayed Aresh
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Abstract
Aggressive voltage and frequency scaling schemes applied to memory and cache structures, specially for memory systems fabricated in advanced and scaled geometry nodes that are severely affected by process variation,significantly increases the likelihood of read, write and access failures to/from memory cell array, and reduces the extent of frequency and voltage scaling. To remedy this problem, in the past decade, many researchers have investigated alternative and fault tolerant cache and memory organizations to mitigate the impact of process variation, and to reduce the failure rate of memory array in the results of voltage and frequency scaling. This paper discusses and compare many of such cache and memory design techniques.
Description
This paper is a survey paper on such fault and variation tolerant techniques. The rest of this paper is organized as follows: in section two we divide the various process variation mitigation techniques into three major categories and describe each category in the following sections three to five. Sections three to five describe the body of papers and techniques that could be categorized under each of these categories. In section six we describe the metrics used for evaluation and benchmarking of the suggested solutions. Section seven describes innovative solutions for process variation management. Finally, in section eight this survey paper is concluded.
Keywords
Process variation, Fault tolerant memory, Fault tolerant cache, DVFS