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Compact Modeling of Multi Gate and Other Emerging Transistors

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dc.contributor.advisor Ioannou, Dimitris E.
dc.contributor.author Donizetti, Matthew Thomas
dc.creator Donizetti, Matthew Thomas
dc.date 2010-11-30
dc.date.accessioned 2011-02-21T21:56:14Z
dc.date.available NO_RESTRICTION en_US
dc.date.available 2011-02-21T21:56:14Z
dc.date.issued 2011-02-21
dc.identifier.uri https://hdl.handle.net/1920/6174
dc.description.abstract With the advent of multi gate and nanoscale fabrication techniques, several new transistor topographies have been proposed and manufactured in the past decade. In parallel, accurate and efficient compact models for these devices have been likewise developed. This paper summarizes the major topographies and their associated compact models with a focus toward computationally efficient models constructed for implementation in common modeling languages such as Verilog-A and SPICE. Common physical and mathematical modeling techniques have also been reviewed as has the evolution from simple multi gate devices to nanoscale structures.
dc.language.iso en_US en_US
dc.subject ballistic en_US
dc.subject overview en_US
dc.subject solid state en_US
dc.subject BSIM en_US
dc.subject survey en_US
dc.subject SPICE en_US
dc.title Compact Modeling of Multi Gate and Other Emerging Transistors en_US
dc.type Thesis en
thesis.degree.name Master of Science en_US
thesis.degree.level Master's en
thesis.degree.discipline Electrical Engineering en
thesis.degree.grantor George Mason University en


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