Performance-Aware Coarse-Grained Reconfigurable Logic Accelerator for Deep Learning Application
| dc.contributor.advisor | Pudukotai Dinakarrao, Sai Manoj | |
| dc.contributor.author | Mercado Rejas, Katherine | |
| dc.creator | Mercado Rejas, Katherine | |
| dc.date | 2022-08-04 | |
| dc.date.accessioned | 2023-04-04T14:10:49Z | |
| dc.date.available | 2023-04-04T14:10:49Z | |
| dc.description.abstract | Deep neural networks (DNNs) are widely deployed in various cognitive applications including computer vision, speech recognition, and image processing. The surpassing accuracy and performance of deep neural networks come at the cost of high computational complexity. Therefore, software implementations of DNNs and convolutional neural networks (CNNs) are often hindered by computational and communication bottlenecks. As a panacea, numerous hardware accelerators are introduced in recent times to accelerate DNNs and CNNs. Despite effectiveness, the existing hardware accelerators are often confronted by the involved computational complexity and the need for special hardware units to implement each of the DNN/CNN operations.To address such challenges, a reconfigurable DNN/CNN accelerator is proposed in this work. The proposed architecture comprises nine processing elements (PEs) that can perform both convolution and arithmetic operations, through run-time reconfiguration with minimal overhead. To reduce the computational complexity, we employ Mitchell's algorithm, which is supported through low-overhead coarse-grained reconfigurability in this work. To facilitate efficient data flow across the PEs, we pre-compute the dataflow paths and configure the dataflow during the runtime. The proposed design is realized on a field-programmable gate array (FPGA) platform for evaluation. | |
| dc.identifier.uri | https://hdl.handle.net/1920/13229 | |
| dc.language.iso | en | |
| dc.subject | Hardware accelerator | |
| dc.subject | Deep neural networks | |
| dc.subject | VLSI | |
| dc.subject | FPGA | |
| dc.subject | Reconfigurable architecture | |
| dc.subject | Convolutional neural networks | |
| dc.title | Performance-Aware Coarse-Grained Reconfigurable Logic Accelerator for Deep Learning Application | |
| dc.type | Thesis | |
| thesis.degree.discipline | Electrical Engineering | |
| thesis.degree.grantor | George Mason University | |
| thesis.degree.level | Master's | |
| thesis.degree.name | Master of Science in Electrical Engineering |