Physics and Design of SOI FED Based Memory Cells
Date
2016
Authors
Badwan, Ahmad Zuhdi
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Abstract
Memory arrays occupy a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory (6T-SRAM) and the single transistor dynamic random access memory (DRAM) cells both suffer from excessive leakage current. Therefore, there is a widely recognized need for urgent progress in memory technology to meet the increasing demand for highly for compact, high density and low power memory arrays.
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Keywords
Electrical engineering, DRAM, FED, Field effect diode, SRAM, Thyristor